The present invention relates to an inductive load driving circuit that drives inductive load, using switching elements that are formed in an integrated circuit device.
A disk media apparatus, such as a CD, CD-ROM, DVD and MD, is provided with an inductive load, such as, an actuator and a motor. The load is driven by a load driving circuit that uses semiconductor switching devices as control devices, such as MOSFETs (insulation gate field effect transistors), bipolar transistors and the like.
FIGS. 1A and 1B show a conventional inductive load driving circuit that has generally been used, which is formed in an integrated circuit device.
Referring to FIG. 1, load driving MOSFETs Q1 through Q4 that are N-channel type and a load L are formed in a bridge circuit. A control circuit 11 provides a driving signal 12 that is composed of a PWM (pulse width modulation) control signal and forward and inverse direction control signals to thereby control the driving circuit.
When the load L is driven in a forward direction, the MOSFET Q1 is controlled to be conductive by the PWM control signal, and the MOSFET Q4 is controlled to be conductive by the forward direction control signal, such that a load current in a forward direction flows through the load L. Inversely, when the load L is driven in an inverse direction, the MOSFET Q2 is controlled to be conductive by the PWM control signal, and the MOSFET Q3 is controlled to be conductive by the inverse direction control signal, such that a load current in an inverse direction flows through the load L.
FIG. 1 shows the case when the load L is driven in an inverse direction. In this case, the MOSFET Q3 is turned on by the inverse direction control signal, and the MOSFET Q2 is turned on and off by the PWM control signal. In this instance, the MOSFET Q1 and the MOSFET Q4 are turned off.
When the MOSFET Q2 is turned on by the PWM control signal, and driven simultaneously with the MOSFET Q3, a load current Io in an inverse direction (shown in a dot-and-dash line in FIG. 1) flows through the load L, in a direction from a power supply potential point Vcc to a ground potential point GND, as shown in FIG. 1A.
On the other hand, when the MOSFET Q2 is turned off by the PWM control signal, only the MOSFET Q3 turns on, as shown in FIG. 1B. As described above, the MOSFET Q4 is an N-channel type. Therefore, when the MOSFET Q4 is in an OFF state, a current path is formed by a parasitic diode that is formed by a back gate BG connected to a source S, a P-type substrate and an N-type drain D, and a current could flow through.
Since the load L is an inductive load such as a motor and an actuator, a load current Io circulates through a path that is formed by the load L, drain and source of the MOSFET Q3, the source S, the back gate BG and the drain D of the MOSFET Q4 (namely, a parasitic diode), as shown by a dot-and-dash line in the figure, by an inductive electromotive force by the accumulated energy of the inductive load L.
As a result, when the MOSFET Q2 is turned on and off by the PWM control signal, the load current Io continuously flows in accordance the duty ratio of the PWM control signal.
At this moment, a parasitic NPN-type bipolar transistor is formed in the integrated circuit device in which the inductive load driving circuit is formed. The parasitic NPN-type bipolar transistor has a base that is an anode side (i.e., the back gate BG of the MOSFET Q4) of the parasitic diode and an emitter that is a cathode side (i.e., the drain D of the MOSFET Q4) of the parasitic diode. The parasitic NPN-type bipolar transistor draws a current from an N-type semiconductor that is formed in another region depending on the direct current amplification coefficient hfe of the parasitic NPN-type bipolar transistor.
Normally, when the parasitic transistor draws a current from an N-type semiconductor of an element that forms another circuit, the circuit is possibly malfunctioned. Therefore, an N-type semiconductor guardring is disposed around the switching transistor (in this case, the MOSFETs Q4 and Q3). The N-type semiconductor guardring is connected to a stable high potential such as the power supply potential point Vcc to thereby supply a current to the parasitic transistor and reduce effects by the parasitic transistor on the other circuit outside the guardring.
However, when the parasitic NPN-type bipolar transistor is turned on, power is consumed not only between the base and the emitter of the parasitic NPN-type bipolar transistor, but also between the collector and the emitter thereof. Since the collector is connected to a high potential of the power supply potential point Vcc, a large loss is generated by the collector current. Also, with a higher switching frequency of the PWM control, the loss becomes greater. Such a loss cannot be neglected.
An inductive load driving circuit is formed in an integrated circuit device having a first switching transistor, a second switching transistor, and a guardring. The first switching transistor is connected between a first power supply potential point and an output terminal. The second switching transistor is connected between the output terminal and a second power supply potential point. The first switching transistor and the second switching transistor are controllably turned on and off, to thereby supply an adjusted power to an inductive load that is connected between the output terminal and the second power supply potential point. A guardring of an N-type semiconductor region is provided for the second switching transistor. The guardring is connected to the second power supply potential point.
In the inductive load driving circuit, the second switching transistor may be an N-channel MOSFET having a back gate region and a drain region where the N-channel MOSFET is formed in a P-type semiconductor substrate. Also, the second switching transistor may be an N-channel DMOSFET having a drain region where the N-channel DMOSFET is formed in an N-type diffusion layer provided in a type semiconductor substrate. In addition, the second switching transistor may be an NPN-type bipolar transistor formed in an N-type diffusion layer provided in a type semiconductor substrate.
In this manner, the circuit has the first and the second switching transistors that are connected between the first power supply potential point and the second power supply potential point, and controllably turned on and off to drive the inductive load. The circuit is provided with the guardring that prevents effects on other elements formed on the same semiconductor substrate, and the guardring is connected to the second power supply potential point. By this structure, a load current in an inverse direction flows via a parasitic diode of the second switching transistor that is provided on the side of the ground and is in an off state. Other effects similar to those described above are also achieved.